MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 343
CHAPTER 19 16-BIT PPG TIMER
19.6 Operations and Setting Procedure Example
■ Hardware Trigger
"Hardware trigger" refers to PPG activation by signal input to the TRGn input pin. When
EGS1 and EGS0 are set to "0b11" and the hardware trigger is used with TRGn input, PPG
starts operation on a rising edge and halts the operation upon the detection of a falling edge.
Moreover, the PPG timer begins operation of the following rising edge from the beginning.
The operation can be retriggered by a valid TRGn input hardware trigger regardless of the
retrigger setting of the RTRG bit when the TRGn input hardware trigger has been selected.
Figure 19.6-5 Hardware Trigger in PWM Mode
■ Setting Procedure Example
Below is an example of procedure for setting the 16-bit PPG timer.
● Initial setup
1. Set the interrupt level. (ILR*)
2. Enable the hardware trigger and interrupts, select the interrupt type, and enable output.
(PCNTLn)
3. Select the count clock and the mode, and enable timer operation. (PCNTHn)
4. Set the cycle. (PCSRHn, PCSRLn)
5. Set the duty. (PDUTHn, PDUTLn)
6. Start the PPG by the software trigger. (PCNTHn:STRG = 1)
*: For details of the interrupt level setting register (ILR), refer to "CHAPTER 5 INTERRUPTS" in this
hardware manual and "■ INTERRUPT SOURCE TABLE" in the device data sheet.
● Interrupt processing
1. Process any interrupt.
2. Clear the interrupt request flag. (PCNTLn:IRQF)
m
n
0
(1)=n × T ns
(2)=m × T ns
PPG
PPG
(1)
(2)
(Normal polarity)
(Inverted polarity)
Time
Counter value
Hardware trigger
Falling edge detected
Rising edge detected
n: Value of PDUTH & PDUTL registers
m: Value of PCSRH & PCSRL registers
T : Count clock cycle
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