MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 401
CHAPTER 21 MULTI-PULSE GENERATOR
21.5 Operations
Setting the 16-bit MPG output data buffer register 0 (upper/lower) (OPDBRH0/OPDBRL0)
(No. 0) as shown in Table 21.5-3 initializes the value of the 16-bit MPG output data register
(upper/lower) (OPDUR/OPDLR). The following sequence begins to operate according to the
write timing generated:
No. 4 -> No. 6 -> No. 2 -> No. 3 -> No. 1 -> No. 5 -> No. A -> No. B -> No. 9 -> No. 4 and
recycle.
The data is transferred to the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR)
sequentially. The 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/
OPDBRLx) are not used if it is not set, e.g. No. 7 and No. 8 in Table 21.5-3.
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