MB95630H Series
444 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 21 MULTI-PULSE GENERATOR
21.6 Registers
[bit2] SEE2: SNI2 enable bit
This bit enables or disables the edge detection on the SNI2 pin.
Set this bit before setting the CMPE bit in the input control register (upper) (IPCUR) to "0".
[bit1] SEE1: SNI1 enable bit
This bit enables or disables the edge detection on the SNI1 pin.
Set this bit before setting the CMPE bit in the input control register (upper) (IPCUR) to "0".
[bit0] SEE0: SNI0 enable bit
This bit enables or disables the edge detection on the SNI0 pin.
Set this bit before setting the CMPE bit in the input control register (upper) (IPCUR) to "0".
bit2 Details
Writing "0" Disables the edge detection on the SNI2 pin.
Writing "1" Enables the edge detection on the SNI2 pin.
bit1 Details
Writing "0" Disables the edge detection on the SNI1 pin.
Writing "1" Enables the edge detection on the SNI1 pin.
bit0 Details
Writing "0" Disables the edge detection on the SNI0 pin.
Writing "1" Enables the edge detection on the SNI0 pin.