MB95630H Series
458 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 22 UART/SIO
22.2 Configuration
● UART/SIO serial mode control register 1 ch. n (SMC1n)
This register controls UART/SIO operation mode. It is used to set the serial data direction
(endian), parity and its polarity, stop bit length, operation mode (synchronous/asynchronous),
data length, and serial clock.
● UART/SIO serial mode control register 2 ch. n (SMC2n)
This register controls UART/SIO operation mode. It is used to enable/disable serial clock
output, serial data output, transmission/reception, and interrupts and to clear the receive error
flag.
● UART/SIO serial status and data register ch. n (SSRn)
This register indicates the transmission/reception status and error status of UART/SIO.
● UART/SIO serial input data register ch. n (RDRn)
This register holds the receive data. The serial input is converted and then stored in this
register.
● UART/SIO serial output data register ch. n (TDRn)
This register sets the transmit data. Data written to this register is serial-converted and then
output.
■ Input Clock
The UART/SIO uses the output clock (internal clock) from the dedicated baud rate generator or
the input signal (external clock) from the UCKn pin as its input clock (serial clock).