MB95630H Series
520 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 24 I
2
C BUS INTERFACE
24.7 Registers
Notes:
• When clearing the interrupt request flag bit (IBCR1n:BER) by writing "0" to it, do not
update the interrupt request enable bit (IBCR1n:BEIE) at the same time.
• All bits in the IBCR1n register except the BER and BEIE bits are cleared to "0" either
when the I
2
C bus interface operation is disabled (ICCRn:EN = 0) or when a bus error
occurs (IBCR1n:BER = 1).
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