Fujitsu 8FX

MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 527
CHAPTER 24 I
2
C BUS INTERFACE
24.7 Registers
[bit4:3] CS[4:3]: Clock-1 select bits (Divider m)
[bit2:0] CS[2:0]: Clock-2 select bits (Divider n)
These bits set the shift clock frequency.
The shift clock frequency (Fsck) is set by the following equation:
Fsck =
φ represents the machine clock frequency (MCLK).
Note:
If the standby mode wakeup function is not used, disable the I
2
C bus interface operation
before making the MCU transit to stop mode or watch mode.
bit4:3 Details
Writing "00" 5
Writing "01" 6
Writing "10" 7
Writing "11" 8
bit2:0 Details
Writing "000" 4
Writing "001" 8
Writing "010" 22
Writing "011" 38
Writing "100" 98
Writing "101" 128
Writing "110" 256
Writing "111" 512
φ
(m × n + 2)