Fujitsu 8FX

MB95630H Series
40 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 3 CLOCK CONTROLLER
3.4 Clock Modes
(13)
Sub-CR clock
Main CR clock/
Main CR PLL
clock
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b110", the device transits to main CR clock mode after waiting for the
main CR clock oscillation stabilization wait time.
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b111", the device transits to main CR PLL clock mode after waiting for the
main CR PLL clock oscillation stabilization wait time.
(14) Main clock
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b010", the device transits to main clock mode after waiting for the main
clock oscillation stabilization wait time.
(15)
Subclock Same as (3) and (4)
(16)
(17)
Subclock
Main CR clock/
Main CR PLL
clock
Same as (13)
(18) Main clock Same as (14)
(19)
Sub-CR clock Same as (1) and (2)
(20)
Table 3.4-1 Clock Mode State Transition Table (2 / 2)
Current
State
Next State Description