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GEN7iB

285

GEN series SYNCHRONIZATION METHODS

HBM systems use the following details for BMC:

BMC settings GEN DAQ mainframaes

Model GEN3i/GEN3iA/GEN7i/

GEN7iA/GEN7iB

GEN2tB/GEN4tB/GEN7tA

GEN7tB/GEN17tA/GEN17B

QuantumX

(B hardware)

Priority 1 128 128

Class 248 248

Accuracy FE FE

Variance FFFF FFFF

Priority 2 122 128

When using any of the HBM systems listed in this table, the systems in the leftmost

column are granted Master rights based on the BMC algorithm.

Adjustments to synchronize to an external clock result in small deviations of the

sample period. Technically speaking, this could be seen as jitter on the ADC clock.

Depending on the jitter value, this results in noise, especially during frequency domain

evaluations (FFT).

If sample rates are higher, the small corrections are relatively large compared to the

same adjustment to sample rates that are 100 times lower. Therefore, the faster sam-

pling systems are prioritized within the HBM range to become clock master.

Tip

For each eld, the smallest value will wins. For example, if Priority 1 for System A is smaller

when compared to System B, all the other elds are no longer monitored/analyzed, as the

weight of the rst eld outweighs all other elds.

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HBK GEN7iB GEN Series Specifications

General