Honeywell Series A - Page 356

8. Maintenance, Checkout, and Calibration
8.10. FIM Self-Test Diagnostic Codes
356 Experion PKS Series A Fieldbus Interface Module User's Guide R400
Honeywell July 2010
Test Code Target Device(s) Failure Modes Function
e) Looking at the address to see
that it changed and the
correct data was written
.
T114
ICP Clock Run Test
ICP ASIC, PLD,
ICP Oscillator
Verify that ICP ASIC timer register
changes.
T115
ICP Clock Compare
Test
CPU, Oscillator,
PLD, ICP ASIC,
ICP Oscillator
Check the ASIC clock against the
CPU clock to make sure they are
running at the same relative rates.
The ICP ASIC read timer
command is used to write the
internal timer to shared RAM
where it is read by the CPU.
T116
ICP ASIC Timer
Interrupt Test
CPU, PLD, ICP
ASIC
The ICP ASIC timer interrupt is
enabled and a timer started to
allow it to generate an interrupt on
IRQ2. The ASIC timer is disabled
after the test.
T118
ICP RAM Test
CPU, PLD, ICP
ASIC
A different set of pattern tests from
zero up and verify, and from -1
down and verify; for byte,
halfword, word.
Fieldbus Interface Module Diagnostics
T120
FPGA Load Test FPGA , CPU
Brings FPGA out of reset, verifies
no error, and loads bit image
serially. Verifies configuration
complete without error.
T121
Lower Byte Access
Test
FPGA, CPU, RAM
Verifies that lower RAM segment
can be accessed as 8-bit values.
T122
Upper Byte Access
Test
FPGA, CPU, RAM
Verifies that upper RAM segment
can be accessed as 8-bit values.
T123
Lower RAM Parity
Test
FPGA, CPU, RAM
Verifies that an odd and even RAM
parity error can be generated and
detected on each byte lane of the
lower RAM segment.
T124
Upper RAM Parity
Test
FPGA, CPU, RAM
Verifies that an odd and even RAM
parity error can be generated and