HP 1660 Series User Manual

Performance Test Record (continued)
Test Settings Results
Single-Clock,
Single-Edge
Acquisition
Pass/Fail Pass/Fail
All Pods,
Channel 3
Setup/Hold Time 3.5/0.0 ns J↑
K↑
L↑
M↑
N↑
P↑
________
________
________
________
________
________
J↓
K↓
L↓
M↓
N↓
P↓
________
_________
________
________
________
________
Setup/Hold Time 0.0/3.5 ns J↑
K↑
L↑
M↑
N↑
P↑
________
________
________
________
________
________
J↓
K↓
L↓
M↓
N↓
P↓
________
_________
________
________
________
________
Setup/Hold Time 1.5/2.5 ns J↑
K↑
L↑
M↑
N↑
P↑
________
_________
________
________
________
________
J↓
K↓
L↓
M↓
N↓
P↓
________
_________
________
________
________
________
All Pods,
Channel 11
Setup/Hold Time 3.5/0.0 ns J↑
K↑
L↑
M↑
N↑
P↑
________
_________
________
________
________
________
J↓
K↓
L↓
M↓
N↓
P↓
________
_________
________
________
________
________
Setup/Hold Time 0.0/3.5 ns J↑
K↑
L↑
M↑
N↑
P↑
________
_________
________
________
________
________
J↓
K↓
L↓
M↓
N↓
P↓
________
_________
________
________
________
________
Setup/Hold Time 1.5/2.5 ns J↑
K↑
L↑
M↑
N↑
P↑
________
_________
________
________
________
________
J↓
K↓
L↓
M↓
N↓
P↓
________
_________
________
________
________
________
Performance Test Record (logic analyzer)
3–97

HP 1660 Series Specifications

General

Category	Logic Analyzer
Glitch Trigger	Yes
Pattern Trigger	Yes
State Analysis	Yes
Transitional Timing	Yes
Trigger Modes	Edge, Pattern, Glitch