HP 1660 Series User Manual

Performance Test Record (continued)
Test Settings Results
Multiple-Clock,
Multiple-Edge
Acquisition
Enable pulse generator, channel 2
COMP (LED on)
Disable pulse generator,
channel 2 COMP (LED off)
Pass/Fail Pass/Fail
All Pods,
Channel 3
Setup/Hold Time 4.5/0.0 ns J↑ + M↓ + N↑
K↑ + L↓ + P↑
________
________
J↓ + M↑ + N↓
K↓ + L↑ + P↓
________
________
Setup/Hold Time 0.0/4.5 ns J↑ + M↓ + N↑
K↑ + L↓ + P↑
________
________
J↓ + M↑ + N↓
K↓ + L↑ + P↓
________
________
Setup/Hold Time 2.0/2.5 ns J↑ + M↓ + N↑
K↑ + L↓ + P↑
________
________
J↓ + M↑ + N↓
K↓ + L↑ + P↓
________
________
All Pods,
Channel 11
Setup/Hold Time 4.5/0.0 ns J↑ + M↓ + N↑
K↑ + L↓ + P↑
________
________
J↓ + M↑ + N↓
K↓ + L↑ + P↓
________
________
Setup/Hold Time 0.0/4.5 ns J↑ + M↓ + N↑
K↑ + L↓ + P↑
________
________
J↓ + M↑ + N↓
K↓ + L↑ + P↓
________
________
Setup/Hold Time 2.0/2.5 ns J↑ + M↓ + N↑
K↑ + L↓ + P↑
________
________
J↓ + M↑ + N↓
K↓ + L↑ + P↓
________
________
Performance Test Record (logic analyzer)
3–98

HP 1660 Series Specifications

General

Category	Logic Analyzer
Glitch Trigger	Yes
Pattern Trigger	Yes
State Analysis	Yes
Transitional Timing	Yes
Trigger Modes	Edge, Pattern, Glitch