HP 1660 Series User Manual

Performance Test Record (continued)
Test Settings Results
Single-Clock,
Multiple-Edge
Acquisition
Disable pulse generator,
channel 1 COMP (LED off)
Enable pulse generator,
channel 1 COMP (LED on)
Pass/Fail Pass/Fail
All Pods,
Channel 3
Setup/Hold Time 4.0/0.0 ns J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
_______
J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
_______
Setup/Hold Time 0.0/4.0 ns J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
_______
J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
_______
Setup/Hold Time 2.0/2.0 ns J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
All Pods,
Channel 11
Setup/Hold Time 4.0/0.0 ns J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
Setup/Hold Time 0.0/4.0 ns J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
_______
J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
_______
Setup/Hold Time 2.0/2.0 ns J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
_______
J↕
K↕
L↕
M↕
N↕
P↕
_______
_______
_______
_______
_______
_______
Performance Test Record (logic analyzer)
3–99

HP 1660 Series Specifications

General

Category	Logic Analyzer
Glitch Trigger	Yes
Pattern Trigger	Yes
State Analysis	Yes
Transitional Timing	Yes
Trigger Modes	Edge, Pattern, Glitch