Analyzer Tests (Analy PV)
The analyzer t est s are funct ional performance verificat ion t ests. There are three t ypes of
analyzer tests: the Board Test, the Chip Tests, and the Data Input Inspection. The following
describes the analyzer self-t est s:
Board TestBoard Test
The Board Test functionally verifies the two oscillators and the 9-channel comparators on the
circuit board. First, the oscillators are checked using the event counter on one of the
acquisition ICs. The event counter will count the number of oscillator periods within a
pre-determined time window. The count of oscillator periods is then compared with a known
value.
The comparators are then checked by varying the threshold voltage and reading the state of
the activity indicators. The outputs of the octal DAC are set to the upper voltage limit and
the activity indicators for all of the pod channels are read to see if they are all in a low state.
The octal DAC outputs are then set to the lower voltage limit, and the activity indicators are
read to see if they are in a high state. The DAC outputs are then set to 0.0 V, allowing the
comparators to recognize the test signal being routed to the test input pin of all of the
comparators. Consequently, the activity indicators are read to see if they show activity on all
channels of all of the pods.
Chip TestsChip Tests
During t he Chip Test s, six t est s are performed on t he acquisit ion ICs. The t ests are t he
Communications, Memory, Encoder, Resource, Sequencer, and Clock Generation Tests.
Communications TestCommuni cat i ons Test The communications test verifies that communications pipeline
between the various subsystems of the IC are operating. Checkerboard patterns of "1s"
and "0s" are routed to the address and data buses and to the read/write registers of each
chip. After verifying the communications pipelines, the acquisition clock synchronization
signals that are rout ed from IC t o IC are checked. Finally, t he IC mast er clock
optimization path is checked and verified.
Passing the communications test implies that the communications pipelines running from
subsystem to subsystem on the acquisition IC are functioning and that the clock optimization
circuit on t he IC is funct ioning. Also, passing this t est implies t hat t he acquisit ion clock
synchr onizat ion signals are funct ioni ng and appear at t he synchronizat ion signal out put pins
of the acquisition IC.
Memory TestMemory Test Acquisition RAM is checked by filling the IC RAM with a checkerboard
pattern of "1s" and "0s," then reading each memory location and comparing the test
pattern with known values. Then, the IC RAM is filled with an inverse checkerboard
pattern, read, and compared with known values.
Passing the memory test implies that the acquisition IC RAM is functioning and that each
memory location bit can hold either a logical "1" or logical "0."
Encoder TestEncoder Test The encoder in the FISO front end is tested and verified using a walking
"1" and walking "0" pattern. The walking "1" and "0" is used to stimulate all of the
encoder output pins which connect directly to the FISO memory cells. Additionally, the
post-store counter in each of the acquisition ICs is tested.
Passing the encoder test implies that the FISO encoder is functioning and can properly route
t he acquired data to t he acquisit ion memory FISO RAM. Also, passing t his t est implies t hat
the post-store counter on the acquisition ICs is functioning.
Theory of Operation
Analyzer Tests (Analy PV)
8–16
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