Logic Acquisition Board TheoryLogic Acquisition Board Theory
ProbingProbing
The probing circuit includes the probe cable and terminations. The probe cable consists of
two 17-channel pods which are connected to the circuit board using a high-density
connector. Sixteen single-ended data channels and one single-ended clock/data channel are
passed t o the circuit board per pod.
If the clock/data channel is not used as a state clock in state acquisition mode, it is available
as a dat a channel. The clock/data channel is also available as a dat a channel in t iming
acquisition mode. Eight ( HP 1660A) , six ( HP 1661A) , four ( HP 1662A) , or two (1663A)
clock/data channels are available as data channels, however only six clock/data channels can
be assigned as clock channels in the HP 1660A and HP 1661A. All clock data channels
available in the HP 1662A and HP 1663A can be assigned as clock channels.
The cables use nichrome wire woven in polyarmid yarn for reliability and durability. The
pods also include one ground path per channel in addition to a pod ground. The channel
grounds are configured such that their electrical distance is the same as the electrical
distance of the channel.
The probe tip assemblies and termination modules connected at the end of the probe cables
have a divide-by-10 RC network that reduces the amplitude of the data signals as seen by the
circuit board. This adds flexibility to the types of signals the circuit board can read in
addition to improving signal integrity.
The t erminat ions on t he circuit board are resist ive t erminations that reduce t ransmission line
effect s on the cable. The t erminations also improve signal int egrit y to t he comparators by
matching the impedance of the probe cable channels with the impedance of the signal paths
of the circuit board. All 17 channels of each pod are terminated in the same way. The signals
are still reduced by a factor of 10.
ComparatorsComparators
Two proprietary 9-channel comparators per pod interpret the incoming data and clock
signals as either high or low depending on where the user-programmable t hreshold is set.
The threshold voltage of each pod is individually programmed, and the voltage selected
applies to the clock channel as well as the data channels of each pod.
Each of the comparator ICs has a serial test input port used for testing purposes. A test bit
pattern is sent from the Test and Clock Synchronization Circuit to the comparator. The
comparators t hen propagat e t he t est signal on each of t he nine channels of t he comparator.
Consequently, all data and clock channel pipelines on the circuit board can be tested by the
operat ing syst em soft ware from t he comparator.
AcquisitionAcquisition
The acquisition circuit is made up of a single HP proprietary ASIC. Each ASIC is a
34-channel state/t iming analyzer, and one such ASIC is included for every two logic analyzer
pods. All of the sequencing, pattern/range recognition, and event counting functions are
performed on board the IC.
In addition to the storage qualification and counting functions, the acquisition ASICs also
perform master clocking functions. All six state acquisition clocks are fed to each IC, and
the ICs generate their own sample clocks. Every time you select RUN, the ICs individually
perform a clock optimization before data is stored.
Theory of Operation
The Logic Acquisition Board
8–7
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