Clock optimization involves using programmable delays on board the IC to position the
master clock transition where valid data is capt ured. This procedure greatly reduces the
effects of channel-to-channel skew and other propagation delays.
In the timing acquisition mode, an oscillator-driven clock circuit provides a four-phase,
100-MHz clock signal to each of the acquisition ICs. For high speed timing acquisition
( 100 MHz and faster) , the sample period is determined by the four-phase, 100-MHz clock
signal.
For slower sample rates, one of the acquisition ICs divides the 100-MHz clock signal to the
appropriate sample rate. The sample clock is then fed to all acquisition ICs.
ThresholdThreshold
A precision octal DAC and precision op amp drivers make up the threshold circuit. Each of
the eight channels of the DAC is individually programmable which allows you to set the
thresholds of the individual pods. The 16 data channels and the clock channel of each pod
are all set to the same threshold voltage.
Test and Clock Synchronization CircuitTest and Clock Synchronization Circuit
ECLinPS (TM) ICs are used in the Test and Clock Synchronization Circuit for reliability and
low channel-to-channel skew. Test patt erns are generat ed and sent to t he comparat ors
during soft ware operation verificat ion. The t est pat terns are propagated across all dat a and
clock channels and read by the acquisition ASIC to ensure both the data and clock pipelines
are operat ing corr ect ly.
The Test and Clock Synchronization Circuit also generates a four-phase, 100-MHz
sample/synchronization signal for the acquisition ICs operating in the timing acquisition
mode. The synchronizing signal keeps the internal clocking of the individual acquisition
ASICs locked in st ep wit h t he other ASICs at fast sample rat es. At slower sample rat es, one
of the acquisition ICs divides the 100-MHz clock signal to the appropriate sample rate. The
slow speed sample clock is then used by all acquisition ICs.
Theory of Operation
The Logic Acquisition Board
8–8
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