HP 1660 Series User Manual

Oscilloscope Board Theory (HP 1660AS series only)Oscilloscope Board Theory (HP 1660AS series only)
At t enuat or/Preamp Theory of OperationAt t enuat or/Preamp Theory of Operation
The channel signals are conditioned by the attenuator/preamps, thick film hybrids containing
passive att enuators, impedance convert ers, and a programmable amplifier. The channel
sensitivity defaults to the standard 1-2-4 sequence (other sensitivities can be set also).
However, t he firmware uses passive at tenuat ion of 1, 5, 25, and 125, with the programmable
preamp, to cover the entire sensitivity range.
The input has a selectable 1 MΩ input impedance with ac or dc coupling or a 50Ω input
impedance wit h dc coupling. Compensat ion for t he passive at t enuat ors is laser t rimmed and
is not adjust able. After t he passive at t enuat ors, t he signal is split int o high-frequency and
low-frequency components. Low frequency components are amplified on the main assembly,
where they are combined with the offset voltage. The ac coupling is implemented in the low
frequency amplifier.
The high- and low-frequency components of the signal are recombined and applied to the
input FET of the preamp. The FET provides a high input impedance for the preamp. The
programmable preamp adjusts the gain to suit the required sensitivity and provides the
output signal to the main assembly. The output signal is then sent to both the t rigger
circuitry and ADC.
Oscilloscope AcquisitionOscilloscope Acquisition
The acquisition circuitry provides the sampling, digitizing, and storing of the signals from the
channel att enuators. The channels are identical. Trigger signals from each channel and the
external triggers synchronize acquisition through the t ime base circuitry. A 100 MHz
oscillator and a time base provide system timing and sample clocking. A voltage-controlled
oscillator (VCO), frequency divider, and digital phase detector provide the sample clock for
higher sample rates. Aft er condit ioning and sampling, t he signals are digitized, t hen st ored in
a hybrid IC cont aining a FISO ( fast in, slow out ) memory.
ADCADC The eight-bit ADC digitizes the channel signal. Digitization is done by
comparators in a flash converter. The sample clock latches the digitized value of the
input to save it so that it can be sent to memory.
FISO MemoryFI SO Memor y 8000 samples of the FISO ( fast in, slow out) memory are used per
measurement per channel. Memory posit ions are not addressed direct ly. The
configuration is a ring which loops continuously as it is clocked. Memory position is
tracked by counting clocks. The clocking rate is the same as the ADC, however the clock
frequency is half that of the ADC since the FISO clocks on both transitions of the clock
period. Data is buffered onto the CPU data bus for processing.
Tr i gger i ngTr i gger i ng There are t wo main trigger circuits that t rigger four t rigger sources. The
two t rigger circuit s are the analog t rigger and the logic trigger. The analog trigger IC
operates as a multichannel Schmidt trigger/comparator. A trigger signal ( a copy of the
analog input signal) from each of the inputs is directed to the analog trigger IC inputs.
The trigger signal is continuously compared wit h the t rigger reference level select ed by
the user. Once t he trigger condition is met, t he trigger TRUE signal is fed to the logic
trigger, which begins the acquisition and store functions by way of the time base.
The four trigger sources are Channel 1, Channel 2, Intermodule Bus ( IMB) , and external
BNC. The operation of the input channels was discussed previously. The IMB trigger signal
is sent directly to the logic trigger. Ext ernal triggering is provided by the BNC input of the
HP 1660-series Logic Analyzer.
Theory of Operation
The Oscilloscope Board
8–10

HP 1660 Series Specifications

General

Category	Logic Analyzer
Glitch Trigger	Yes
Pattern Trigger	Yes
State Analysis	Yes
Transitional Timing	Yes
Trigger Modes	Edge, Pattern, Glitch