Intel P4304XXMFEN2 User Manual

Intel
®
Server Chassis P4304XXMFEN2/P4304XXMUXX Product Family System Integration and Service Guide
158
Diagnostic LED Decoder
LED #
LED 3 LED 2 LED 1 LED 0
Description
Checkpoint
Upper Nibble
8h
(MSB)
4h 2h
1h
(LSB)
Lower Nibble
8h
(MSB)
4h 2h
1h
(LSB)
01h
Upper Nibble
0
0
0
0
First POST code after CPU reset
Lower Nibble
0
0
0
1
02h
Upper Nibble
0
0
0
0
Microcode load begin
Lower Nibble
0
0
1
0
03h
Upper Nibble
0
0
0
0
CRAM initialization begin
Lower Nibble
0
0
1
1
04h
Upper Nibble
0
0
0
0
EI Cache When Disabled
Lower Nibble
0
1
0
0
05h
Upper Nibble
0
0
0
0
SEC Core at Power on Begin
Lower Nibble
0
1
0
1
06h
Upper Nibble
0
0
0
0
Early CPU Initialization during Sec Phase
Lower Nibble
0
1
1
0
UPI RC (Fully leverage without platform change)
A1h
Upper Nibble
1
0
1
0
Collect Info such as SBSP, Boot Mode, Reset Type Etc.
Lower Nibble
0
0
0
1
A3h
Upper Nibble
1
0
1
0
Set Up Minimum Path Between SBSP & Other Sockets
Lower Nibble
0
0
1
1
A7h
Upper Nibble
1
0
1
0
Topology Discovery and Route Calculation
Lower Nibble
0
1
1
1
A8h
Upper Nibble
1
0
1
0
Program Final Route
Lower Nibble
1
0
0
0
A9h
Upper Nibble
1
0
1
0
Program Final IO SAD Setting
Lower Nibble
1
0
0
1
AAh
Upper Nibble
1
0
1
0
Protocol Layer and Other Uncore Settings
Lower Nibble
1
0
1
0
ABh
Upper Nibble
1
0
1
0
Transition Links to Full Speed Operation
Lower Nibble
1
0
1
1
Ach
Upper Nibble
1
0
1
0
PHY Layer Setting
Lower Nibble
1
1
0
0
ADh
Upper Nibble
1
0
1
0
Link Layer Settings
Lower Nibble
1
1
0
1
AEh
Upper Nibble
1
0
1
0

Intel P4304XXMFEN2 Specifications

General

Brand	Intel
Model	P4304XXMFEN2
Category	Chassis
Language	English