How Interrupts Work
Interrupt Flow
How does the interrupt signal reach the CPU?
We’ve just talked about the interrupt flag (IFG) bit – let’s start there. As described on the previous page,
when the interrupt source signal is received, the associated IFG bit is set. In fact, DriverLib contains
functions to read the status of most IFG bits. (Handy in those few cases where you need to poll an interrupt
source.)
When the IFG is set, the MSP430 device now sees that the signal has occurred, but the signal hasn’t made
its way to the CPU, yet. For that to happen, the interrupt must be enabled.
Interrupt enable bits (IE) exist to protect the CPU … and thus, your program. Even with so many peripherals
and interrupt sources, it’s likely that your program will only care about a few of them. The enable bits provide
your program with ‘switches’ that let you ignore all those sources you don’t need.
By default, all interrupt bits are disabled (except the Watchdog Timer). It is your program’s responsibility to
enable those interrupt sources that are needed. To that end, once again, DriverLib provides a set of
functions that make it easy for you to set the necessary IE bits.
Finally, there’s a “master” switch that turns all interrupts off. This lets you turn off interrupts without having to
modify all of the individual IE bits. The MSP430 calls this the global interrupt enable (GIE). It is found in the
MSP430 Status Register (SR).
Why would you need a GIE bit? Sometimes your program may need to complete some code atomically; that
is, your program may need to complete a section of code without the fear that an interrupt could preempt it.
For example, if your program shares a global variable between two threads – say between main() and an
ISR – it may be important to prevent interrupts while the main code reads and modifies that variable.
Note: There are a few non-maskable interrupts (NMI). These sources bypass the GIE bit. These
interrupts are often considered critical events – i.e. ‘fatal’ events – that could be used to provide a
warm reset of the CPU.
IE bit
“Individual”
Int Enable
SR.GIE
“Global”
Int Enable
IFG bit
Interrupt
‘Flag’
CPU
1
TIMER_A
0
GPIO
0
…
0
NMI
Interrupt Flow
Interrupt Enable (IE); e.g.
GPIO_enableInterrupt();
GPIO_disableInterrupt();
TIMER_A_enableInterrupt();
Interrupt Flag Reg (IFR)
bit set when int occurs; e.g.
GPIO_getInterruptStatus();
GPIO_clearInterruptFlag();
Global Interrupt Enable (GIE)
Enables ALL maskable interrupts
Enable: __bis_SR_register( GIE );
Disable: __bic_SR_register( GIE );
Interrupt
Source
MSP430 Workshop - Interrupts 5 - 11
To Next Page
Loading...
Need help?
General
