How Interrupts Work
2. Interrupt is Flagged (and must be Enabled)
When an interrupt signal is received, an interrupt flag (IFG) bit is latched. You can think of this as
the processor’s “copy” of the signal. As some interrupt sources are only on for a short duration, it
is important that the CPU registers the interrupt signal internally.
How do Interrupts Work?
• UART
• GPIO
• Timers
• ADC
• Etc.
1. An interrupt occurs
…currently executing code
interrupt occurs
next_line_of_code
}
2. It sets a flag bit
in a register
. . .
MSP430 devices are designed with “distributed” interrupt management. That is, most IFG bits are
found inside each peripheral’s control registers; this is different from most processors which have
a common, dedicated set of interrupt registers.
The distributed nature of the interrupts provides a number of benefits in terms of device flexibility
and future feature expansion; further, it fits nicely with the low-power nature of the MSP430.
The only ‘negative’ of distributed interrupts might be that it’s different — it’s just that many of us
older engineers are used to seeing all the interrupts grouped together. Bottom line, though, is that
working with interrupts (enabling interrupts, clearing flags, responding to them) is the same
whether the hardware is laid out centrally or in a distributed fashion.
5 - 10 MSP430 Workshop - Interrupts
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