Interrupts: Priorities & Vectors
Interrupt Vector Table
We can expand the previous interrupt source & priority listing to include a few more items. First of
all, we added a column that provides the IV register associated with each interrupt. (Note, the two
names shown in red text represent the IFG bits for dedicated/individual interrupts.)
Additionally, the first 3 rows (highlighted with red background fill) indicate that these interrupt
groups are non-maskable; therefore, they bypass the GIE bit.
Memory Map
0xFFFF
Interrupt Vectors & Priorities (F5529)
The final column in the above diagram hints at the location of each interrupts address vector in
the memory map. For example, when using the WDT as an interval timer, you would put the
address of your appropriate ISR into location “57”. As we saw in a previous topic, this can easily
be done using the vector pragma.
The MSP430 devices reserve the range 0xFFFF to 0xFF80 for the interrupt vectors. This means
that for the ‘F5529, the address for the System Reset interrupt service routine will sit at addresses
0xFFFE – 0xFFFF. (A 16-bit address requires two 8-bit memory locations.) The remaining
interrupt vectors step down in memory from this point. The map to the right of the table shows
where the interrupt vectors appear within the full MSP430 memory map.
MSP430 Workshop - Interrupts 5 - 19
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