Interrupts: Priorities & Vectors
Interrupt Vector (IV) Registers
As has been mentioned a couple of times in this chapter, to make responding to grouped
interrupts easier to handle, the MSP430 team created the concept of Interrupt Vector (IV)
Registers. Reading an IV register will return the highest-priority, pending interrupt in that group; it
will also clear that interrupts associated flag (IFG) bit.
Interrupt Vector (IV) Registers
IV = Interrupt Vector register
Most MSP430 interrupts can be caused by more than one
source; for example:
Each 8-bi GPIO port one has a single CPU interrupt
IV registers provide an easy way to determine which
source(s) actually interrupted the CPU
The interrupt vector register reflects only ‘triggered’
interrupt flags whose interrupt enable bits are also set
Reading the ‘IV’ register:
Clears the pending interrupt flag with the highest priority
Provides an address offset associated with the highest priority
pending interrupt source
An example is provided in the “Coding Interrupts” section
of this chapter
For grouped interrupts, most users read the IV register at the beginning of the ISR and use the
return value to pick the appropriate code to run. This is usually implemented with a Switch/Case
statement. (We will explore an example of this code later in the chapter.)
5 - 18 MSP430 Workshop - Interrupts
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