How Interrupts Work
3. CPU's Hardware Response
At this point, let’s assume you have an interrupt that has: occurred; been flagged; and since it
was enabled, its signal has reached the CPU. What would the CPU do in response to the
interrupt?
Earlier in the chapter we stated: “The interrupt preempts the current thread and starts running the
interrupt service routine (ISR).” While this is true, there are actually a number of items performed
by the hardware to make this happen – as shown below:
How do Interrupts Work?
• UART
• GPIO
• Timers
• ADC
• Etc.
1. An interrupt occurs
…currently executing code
interrupt occurs
next_line_of_code
}
2. Sets a flag bit
(IFG) in register
. . .
3. CPU acknowledges INT by…
• Current instruction completes
• Saves return-to location on stack
• Saves Status Reg (SR) to the stack
• Clears most of SR, which turns off
interrupts globally (SR.GIE=0)
• Determines INT source (or group)
• Clears non-grouped flag
*
(IFG=0)
• Reads interrupt vector & calls ISR
We hope the first 3 items are self-explanatory; the current instruction is completed while the
Program Counter (PC) and Status Register (SR) are written to the system stack. (You might
remember, the stack was setup for the MSP430 by the compiler’s initialization routine. Please
refer to the compiler user’s guide for more information.)
After saving the context of SR, the interrupt hardware in the CPU clears most of the SR bits. Most
significantly, it clears GIE. That means that by default, whenever you enter an ISR function, all
maskable interrupts have been turned off. (We’ll address the topic of ‘nesting’ interrupts in the
next section.)
The final 3 items basically tell us that the processor figures out which interrupt occurred and calls
the associated interrupt service routine; it also clears the interrupt flag bit (if it’s a dedicated
interrupt). The processor knows which ISR to run because each interrupt (IFG) is associated with
an ISR function via a look-up table – called the Interrupt Vector Table.
5 - 12 MSP430 Workshop - Interrupts
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