Interrupts: Priorities & Vectors
Interrupts: Priorities & Vectors
Interrupts and Priorities
Each MSP430 device datasheet defines the pending priority for each of its hardware interrupts. In
the case of the MSP430F5529, there are 23 interrupts shown listed below in decreasing priority.
In the previous paragraph we used the phrase “pending priority” deliberately. As you might
remember from the last topic in this chapter, interrupts on the MSP430 do not nest within each
other by default. This is because the global interrupt (GIE) bit is disabled when the CPU
acknowledges and processes an interrupt. Therefore, if an interrupt occurs while an ISR is being
executed, it will have to wait for the current ISR to finish before it can be handled … even if the
new interrupt is of higher priority.
On the other hand, if two interrupts occur at the same time – that is, if there are two interrupts
currently pending – then the highest priority interrupt is acknowledged and handled first.
Most of the 23 interrupts on the ‘F5529 represent ‘groups’ of interrupts. There are actually 145
interrupt sources – each with their own interrupt flag (IFG) – that map into these 23 interrupts.
For example, the “Timer B (CCIFG0)” interrupt represents a single interrupt signal. When the
CPU acknowledges it, it will clear its single IFG flag.
On the other hand, the next interrupt in line, the “Timer B” interrupt, represents all the rest of the
interrupts that can be initiated by Timer0_B. When any one of the interrupts in this group occurs,
the ISR will need to determine which specific interrupt source occurred and clear its flag (along
with executing whatever code you want to associate with it).
MSP430 Workshop - Interrupts 5 - 17
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