Timer Details: Configuring TIMER_A
Up Mode
The Up counting mode differs from the Continuous mode by resetting back to zero whenever the
counter matches CCR0 (Capture and Compare Register 0).
You can see the different waveforms compared on the slide below. The green waveform
counts Up
to the value found in CCR0, and then resets back to zero.
On the other hand, the grey dotted waveform shows how, when in Continuous mode, the counter
goes past CCR0 and all the way to 0xFFFF.
In Up mode, since we are using the CCR0 register, the timer can actually generate two interrupts:
• CC0IFG (for Timer0_A, this bit is actually called TA0CC0IFG)
• TAIFG (for Timer0_A, this bit is called TA0IFG)
You’re not seeing a color misprint; the two interrupts do not
happen at the exact same time, but
rather 1 cycle apart. The CC0IFG occurs when there is a compare match, while the TA0IFG
interrupt occurs once the counter goes back to zero.
If you compare these two Up mode interrupts to the one generated in the Continuous mode, you’ll
see they occur at a more rapid frequency. This is a big advantage of the Up mode; your
frequency is not limited to 2
16
counts, but rather can be anywhere within the 16-bit counter’s
range. (The downside is that you also have to configure the CCR0 registers.)
Note: The CCR0 (Capture and Control Register 0) is special. That is, it is special in comparison to the
other CCR registers. It is only CCR0 that can be used to define the upper limit of the counter in Up
(or UpDown) count mode.
The other special feature of CCR0 is that it provides a dedicated interrupt (CC0IFG). In other
words, there is an Interrupt Vector location dedicated to CC0IFG. All the other Timer_A interrupts
share a common vector location (i.e. they make up a grouped interrupt).
6 - 16 MSP430 Workshop - Timers
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