List of tables
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts ................................. 12
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts (continued) .............. 13
Table 2. Normal Pin Description ............................................................................................................ 20
Table 2. Normal Pin Description (continued)......................................................................................... 21
Table 2. Normal Pin Description (continued)......................................................................................... 22
Table 3. SFR Map Summary ................................................................................................................. 30
Table 4. XSFR Map Summary .............................................................................................................. 31
Table 5. SFR Map ................................................................................................................................. 32
Table 5. SFR Map (continued) .............................................................................................................. 33
Table 5. SFR Map (continued) .............................................................................................................. 34
Table 5. SFR Map (continued) .............................................................................................................. 35
Table 6. XSFR Map ............................................................................................................................... 36
Table 7. Port Register Map.................................................................................................................... 40
Table 8. Interrupt Vector Address Table ................................................................................................ 56
Table 9. Interrupt Register Map ............................................................................................................. 64
Table 10. Clock Generator Register Map .............................................................................................. 71
Table 11. Basic Interval Timer Register Map ......................................................................................... 74
Table 12. Setting of window open period .............................................................................................. 78
Table 13. Watchdog Timer Register Map .............................................................................................. 78
Table 14. Watch Timer Register Map .................................................................................................... 82
Table 15. Timer 0 Operating Mode ........................................................................................................ 84
Table 16. Timer 0 Register Map ............................................................................................................ 90
Table 17. TIMER 1 Operating Modes .................................................................................................... 92
Table 18. TIMER 1 Register Map ........................................................................................................ 102
Table 19. TIMER 2 Operating Modes .................................................................................................. 105
Table 20. TIMER 2 Register Map ........................................................................................................ 112
Table 21. Buzzer Frequency at 8MHz ................................................................................................. 115
Table 22. Buzzer Driver Register Map ................................................................................................ 116
Table 23. ADC Register Map ............................................................................................................... 120
Table 24. I
2
C Register Map ................................................................................................................. 133
Table 25. Equations for Calculating Baud Rate Register Setting........................................................ 140
Table 26. CPOL Functionality .............................................................................................................. 148
Table 27. Example Condition of RTO .................................................................................................. 151
Table 28. USART Register Map .......................................................................................................... 152
Table 29. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies ....................... 160
Table 30. CRC mode ........................................................................................................................... 162
Table 31. CRC Register Map .............................................................................................................. 163
Table 32. Peripheral Operation Status during Power-down Mode ...................................................... 167
Table 33. Power-down Operation Register Map ................................................................................. 171
Table 34. Hardware Setting Values in Reset State ............................................................................. 172
Table 35. Boot Process Description .................................................................................................... 175
Table 36. Reset Operation Register Map ............................................................................................ 179
Table 37. Flash Control and Status Register Map .............................................................................. 182
Table 38. Program and Erase Time .................................................................................................... 188
Table 39. Operation Mode ................................................................................................................... 195
Table 40. Mode entrance method for ISP ........................................................................................... 195
Table 41. Security Policy using Lock Bits ............................................................................................ 196