Abov A96G166 User Manual

A96G166/A96A166/A96S166 User’s manual 14. I2C
135
I2CSR (I2C Status Register): E2H
7
6
5
4
3
2
1
0
GCALL
TEND
STOP
SSEL
MLOST
BUSY
TMODE
RXACK
R
R
R
R
R
R
R
R
Initial value: 00H
GCALL
This bit has different meaning depending on whether I2C is master
or slave.
NOTE1
When I2C is a master, this bit represents whether it received AACK
(Address ACK) from slave.
When I2C is a slave, this bit is used to indicate general call.
0
No AACK is received (Master mode)
1
AACK is received (Master mode)
0
Received address is not general call address
(Slave mode)
1
General call address is detected (Slave mode)
TEND
This bit is set when 1-Byte of data is transferred completely.
NOTE1
0
1 byte of data is not completely transferred
1
1 byte of data is completely transferred
STOP
This bit is set when STOP condition is detected.
NOTE1
0
No STOP condition is detected
1
STOP condition is detected
SSEL
This bit is set when I2C is addressed by other master.
NOTE1
0
I2C is not selected as slave
1
I2C is addressed by other master and acts as a slave
MLOST
This bit represents the result of bus arbitration in master mode.
NOTE1
0
I2C maintains bus mastership
1
I2C has lost bus mastership during arbitration process
BUSY
This bit reflects bus status.
0
I2C bus is idle, so any master can issue a START
condition
1
I2C bus is busy
TMODE
This bit is used to indicate whether I2C is transmitter or receiver.
0
I2C is a receiver
1
I2C is a transmitter
RXACK
This bit shows the state of ACK signal.
0
No ACK is received
1
ACK is generated at ninth SCL period
NOTES:
1. One of these bits can be a source of an interrupt.
2. When an I2C interrupt occurs except for STOP interrupt, the SCL line is hold
LOW. To release SCL, write arbitrary value to I2CSR.
3. When I2CSR is written, TEND, STOP, SSEL, LOST, RXACK are cleared.

Abov A96G166 Specifications

General

Brand	Abov
Model	A96G166
Category	Computer Hardware
Language	English