14. I2C A96G166/A96A166/A96S166 User’s manual
I2CSCLLR (SCL Low Period Register): E3H
This register defines the LOW period of SCL when I2C operates
in master mode. The base clock is SCLK, the system clock, and
the period is calculated by the formula : t
SCLK
× (4 × SCLL + 1)
where t
SCLK
is the period of SCLK
I2CSCLHR (SCL High Period Register): E4H
This register defines the HIGH period of SCL when I2C operates
in master mode. The base clock is SCLK, the system clock, and
the period is calculated by the formula :t
SCLK
× (4 × SCLH + 3)
where t
SCLK
is the period of SCLK.
So, the operating frequency of I2C master mode (fI2C) is calculated by the following equation.
I2CSDAHR (SDA Hold Time Register): E5H
This register is used to control SDA output timing from the falling
edge of SCL. Note that SDA is changed after t
SCLK
× SDAH. In
master mode, load half the value of SCLL to this register to make
SDA change in the middle of SCL. In slave mode, configure this
register regarding the frequency of SCL from master. The SDA is
changed after t
SCLK
× (SDAH + 4). So, to insure normal operation
in slave mode, the value t
SCLK
× (SDAH + 4) must be smaller
than the period of SCL.
I2CDR (I2C Data Register): E6H
When I2C is configured as a transmitter, load this register with
data to be transmitted. When I2C is a receiver, the received data
is stored into this register.