Abov A96G166 User Manual

Contents A96G166/A96A166/A96S166 User’s manual
4
12.1 Buzzer driver block diagram ............................................................................................. 115
12.2 Register map ..................................................................................................................... 116
12.3 Register description .......................................................................................................... 116
13 12-bit ADC .................................................................................................................................. 117
13.1 Conversion timing ............................................................................................................. 117
13.2 Block diagram ................................................................................................................... 118
13.3 ADC operation................................................................................................................... 119
13.4 Register map ..................................................................................................................... 120
13.5 Register description .......................................................................................................... 120
14 I2C .............................................................................................................................................. 123
14.1 Block Diagram ................................................................................................................... 123
14.2 Bit transfer ......................................................................................................................... 124
14.3 Start/ repeated start/ stop ................................................................................................. 124
14.4 Data transfer ..................................................................................................................... 125
14.5 Acknowledge ..................................................................................................................... 125
14.6 Synchronization/ arbitration .............................................................................................. 126
14.7 Block operation ................................................................................................................. 127
14.7.1 I2C block initialization process ............................................................................. 128
14.7.2 I2C interrupt service ............................................................................................. 129
14.7.3 Master transmitter ................................................................................................ 130
14.7.4 Slave receiver ....................................................................................................... 132
14.8 Register Map ..................................................................................................................... 133
14.9 I2C register description ..................................................................................................... 134
15 USART 0/1 ................................................................................................................................. 138
15.1 Block diagram ................................................................................................................... 139
15.2 Clock generation ............................................................................................................... 140
15.3 External clock (XCK) ......................................................................................................... 141
15.4 Synchronous mode operation ........................................................................................... 141
15.5 Data format ....................................................................................................................... 142
15.6 Parity bit ............................................................................................................................ 143
15.7 USART transmitter ............................................................................................................ 143
15.7.1 Sending Tx data ................................................................................................... 143
15.7.2 Transmitter flag and interrupt ............................................................................... 144
15.7.3 Parity generator .................................................................................................... 144
15.7.4 Disabling transmitter ............................................................................................. 144
15.8 USART receiver ................................................................................................................ 144
15.8.1 Receiving Rx data ................................................................................................ 145
15.8.2 Receiver flag and interrupt ................................................................................... 145
15.8.3 Parity checker ....................................................................................................... 146
15.8.4 Disabling receiver ................................................................................................. 146
15.8.5 Asynchronous data reception ............................................................................... 146
15.9 SPI mode .......................................................................................................................... 148
15.9.1 SPI clock formats and timing ................................................................................ 148
15.10 Receiver time out (RTO) ................................................................................................... 151
15.11 Register map ..................................................................................................................... 152
15.12 Register description .......................................................................................................... 153
15.13 Baud rate settings (example) ............................................................................................ 160
15.14 0% error baud rate ............................................................................................................ 161
16 CRC............................................................................................................................................ 162
16.1 Block Diagram ................................................................................................................... 162

Abov A96G166 Specifications

General

Brand	Abov
Model	A96G166
Category	Computer Hardware
Language	English