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A96G166
Abov A96G166 User Manual
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A96G166/A96A166/A9
6S166 User’s
manual
6
.
Interrupt controller
69
EIPOL2 (External Int
errupt Polarity
2 Registe
r):
A3H
7
6
5
4
3
2
1
0
POLA
POL9
POL8
POL7
R
/
W
R
/
W
R
/
W
R
/
W
R
/
W
R
/
W
R
/
W
R
/
W
Initial value
:
00H
EIPOL2[7:0]
External interrupt (EINTA, EINT9, EINT8, EINT7) polarity selection
POLn[1:0]
Description
0
0
No interrupt at any edge
0
1
Interrupt on rising edge
1
0
Interrupt on falling edge
1
1
Interrupt on both of rising and falling edge
Where n =7
,
8, 9 and A
68
70
Table of Contents
Introduction
1
Reference Document
1
Table of Contents
2
Description
12
Device Overview
12
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts
12
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts (Continued)
13
A96G166/A96A166/A96S166 Block Diagram
14
Figure 1. A96G166/A96A166/A96S166 Block Diagram
14
Pinouts and Pin Description
15
Pinouts
15
Figure 2. A96G166 16SOPN Pin Assignment
15
Figure 3. A96G166 20TSSOP/20SOP Pin Assignment
16
Figure 4 A96A166 20SOP Pin Assignment
16
Figure 5. A96S166 20TSSOP Pin Assignment
17
Figure 6. A96G166 20 QFN Pin Assignment
18
Figure 7. A96G166 28SOP Pin Assignment
19
Figure 8. A96G166 32 LQFP Pin Assignment
19
Pin Description
20
Table 2. Normal Pin Description
20
Table 2. Normal Pin Description (Continued)
21
Table 2. Normal Pin Description (Continued)
22
Port Structures
24
Figure 9. General Purpose I/O Port
24
Figure 10. External Interrupt I/O Port
25
Memory Organization
26
Program Memory
26
Data Memory
27
Figure 11. Program Memory Map
27
Figure 12. Data Memory Map
28
Figure 13. Lower 128Bytes of RAM
28
External Data Memory
29
Figure 14. XDATA Memory Area
29
SFR Map
30
SFR Map Summary
30
Table 3. SFR Map Summary
30
Table 4. XSFR Map Summary
31
SFR Map
32
Table 5. SFR Map
32
Table 5. SFR Map (Continued)
33
Table 5. SFR Map (Continued)
34
Table 5. SFR Map (Continued)
35
Table 6. XSFR Map
36
Compiler Compatible SFR
37
5 I/O Ports
39
Port Register
39
Data Register (Px)
39
Direction Register (Pxio)
39
Pull-Up Register Selection Register (Pxpu)
39
Open-Drain Selection Register (Pxod)
39
Bounce Enable Register (Pxdb)
39
Port Function Selection Register (Pxfsr)
39
Register Map
40
Table 7. Port Register Map
40
P0 Port
41
P0 Port Description
41
Register Description for P0
41
P1 Port
44
P1 Port Description
44
Register Description for P1
44
P2 Port
48
P2 Port Description
48
Register Description for P2
48
P3 Port
50
P3 Port Description
50
Register Description for P3
50
Interrupt Controller
52
Figure 15. Interrupt Group Priority Level
53
External Interrupt
54
Figure 16. External Interrupt Description
54
Block Diagram
55
Figure 17. Interrupt Controller Block Diagram
55
Interrupt Vector Table
56
Table 8. Interrupt Vector Address Table
56
Interrupt Sequence
57
Figure 18. Interrupt Sequence Flow
58
Effective Timing after Controlling Interrupt Bit
59
Figure 19. Case A: Effective Timing of Interrupt Enable Register
59
Figure 20. Case B: Effective Timing of Interrupt Flag Register
59
Multi-Interrupt
60
Figure 21. Effective Timing of Multi-Interrupt
60
Interrupt Enable Accept Timing
61
Interrupt Service Routine Address
61
Saving/Restore General Purpose Registers
61
Figure 22. Interrupt Response Timing Diagram
61
Figure 23. Correspondence between Vector Table Address and the Entry Address of ISR
61
Figure 24. Saving/Restore Process Diagram and Sample Source
61
Interrupt Timing
62
Figure 25. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
62
Interrupt Register Overview
63
Interrupt Enable Register (IE, IE1, IE2, and IE3)
63
Interrupt Priority Register (IP and IP1)
63
External Interrupt Flag Register (EIFLAG0 and EIFLAG1)
63
External Interrupt Polarity Register (EIPOL0L, EIPOL0H, EIPOL1 and EIPOL2)
63
Register Map
64
Table 9. Interrupt Register Map
64
Interrupt Register Description
65
Clock Generator
70
Clock Generator Block Diagram
71
Register Map
71
Figure 26. Clock Generator Block Diagram
71
Table 10. Clock Generator Register Map
71
Register Description
72
Basic Interval Timer
74
BIT Block Diagram
74
BIT Register Map
74
Figure 27. Basic Interval Timer Block Diagram
74
Table 11. Basic Interval Timer Register Map
74
BIT Register Description
75
Watchdog Timer
76
Setting Window Open Period of Watchdog Timer
77
Figure 28. Watch Dog Timer Interrupt Timing Waveform
77
WDT Block Diagram
78
Register Map
78
Figure 29. Watch Dog Timer Block Diagram
78
Table 12. Setting of Window Open Period
78
Table 13. Watchdog Timer Register Map
78
Register Description
79
10 Watch Timer
81
WT Block Diagram
81
Figure 30. Watch Timer Block Diagram
81
Register Map
82
Watch Timer Register Description
82
Table 14. Watch Timer Register Map
82
Timer 0/1/2
84
Timer 0
84
8-Bit Timer/Counter Mode
84
Table 15. Timer 0 Operating Mode
84
Figure 31. 8-Bit Timer/Counter Mode for Timer 0
85
Figure 32. 8-Bit Timer/Counter 0 Example
85
8-Bit PWM Mode
86
Figure 33. 8-Bit PWM Mode for Timer 0
86
Figure 34. PWM Output Waveforms in PWM Mode for Timer 0
87
8-Bit Capture Mode
88
Figure 35. 8-Bit Capture Mode for Timer 0
88
Figure 36. Input Capture Mode Operation for Timer 0
89
Figure 37. Express Timer Overflow in Capture Mode
89
Timer 0 Block Diagram
90
Register Map
90
Figure 38. 8-Bit Timer 0 Block Diagram
90
Table 16. Timer 0 Register Map
90
Register Description
91
Timer 1
92
Table 17. TIMER 1 Operating Modes
92
16-Bit Timer/Counter Mode
93
Figure 39. 16-Bit Timer/Counter Mode of Timer 1
93
Figure 40. 16-Bit Timer/Counter Mode Operation Example
94
16-Bit Capture Mode
95
Figure 41. 16-Bit Capture Mode of Timer 1
95
Figure 42. 16-Bit Capture Mode Operation Example
96
Figure 43. Express Timer Overflow 16-Bit Capture Mode
96
16-Bit PPG Mode
97
Figure 44. 16-Bit PPG Mode of Timer 1
97
Figure 45. 16-Bit PPG Mode Operation Example
98
16-Bit Complementary PWM Mode (Dead Time)
99
Figure 46. 16-Bit Complementary PWM Mode for Timer 1
99
Figure 47. 16-Bit Complementary PWM Mode Timing Chart for Timer 1
100
16-Bit Timer 1 Block Diagram
101
Figure 48. 16-Bit Timer 1 Block Diagram
101
Register Map
102
Register Description
102
Table 18. TIMER 1 Register Map
102
Timer 2
105
Table 19. TIMER 2 Operating Modes
105
16-Bit Timer/Counter Mode
106
Figure 49. 16-Bit Timer/Counter Mode of Timer 2
106
Figure 50. 16-Bit Timer/Counter Mode Operation Example
107
16-Bit Capture Mode
108
Figure 51. 16-Bit Capture Mode of Timer 2
108
Figure 52. 16-Bit Capture Mode Operation Example
109
Figure 53. Express Timer Overflow in Capture Mode
109
16-Bit PPG Mode
110
Figure 54. 16-Bit PPG Mode of Timer 2
110
Figure 55. 16-Bit PPG Mode Operation Example
111
16-Bit Timer 2 Block Diagram
112
Register Map
112
Figure 56. 16-Bit Timer 2 Block Diagram
112
Table 20. TIMER 2 Register Map
112
Register Description
113
12 Buzzer Driver
115
Buzzer Driver Block Diagram
115
Figure 57. Buzzer Driver Block Diagram
115
Table 21. Buzzer Frequency at 8Mhz
115
Register Map
116
Register Description
116
Table 22. Buzzer Driver Register Map
116
13 12-Bit ADC
117
Conversion Timing
117
Block Diagram
118
Figure 58. 12-Bit ADC Block Diagram
118
Figure 59. A/D Analog Input Pin with a Capacitor
118
ADC Operation
119
Figure 60. Control Registers and Align Bits
119
Figure 61. ADC Operation Flow Sequence
119
Register Map
120
Register Description
120
Table 23. ADC Register Map
120
14 I2C
123
Block Diagram
123
Figure 62. I 2 C Block Diagram
123
Bit Transfer
124
Start/ Repeated Start/ Stop
124
Figure 63. Bit Transfer on the I2C-Bus
124
Figure 64. START and STOP Condition
124
Data Transfer
125
Acknowledge
125
Figure 65. Data Transfer on the I2C-Bus
125
Synchronization/ Arbitration
126
Figure 66. Acknowledge on the I2C-Bus
126
Figure 67. Clock Synchronization During Arbitration Procedure
126
Block Operation
127
Figure 68. Arbitration Procedure of Two Masters
127
I2C Block Initialization Process
128
Figure 69. I2C SCL Max Clock, SCL, SDA Settings
128
I2C Interrupt Service
129
Master Transmitter
130
Slave Receiver
132
Register Map
133
Table 24. I 2 C Register Map
133
I2C Register Description
134
Usart 0/1
138
Block Diagram
139
Figure 70. Usartn Block Diagram (N=0, 1)
139
Clock Generation
140
Figure 71. Clock Generation Block Diagram
140
Table 25. Equations for Calculating Baud Rate Register Setting
140
External Clock (XCK)
141
Synchronous Mode Operation
141
Figure 72. Synchronous Mode Xckn Timing (N = 0, 1)
141
Data Format
142
Figure 73. a Frame Format
142
Parity Bit
143
USART Transmitter
143
Sending Tx Data
143
Transmitter Flag and Interrupt
144
Parity Generator
144
Disabling Transmitter
144
USART Receiver
144
Receiving Rx Data
145
Receiver Flag and Interrupt
145
Parity Checker
146
Disabling Receiver
146
Asynchronous Data Reception
146
Figure 74. Start Bit Sampling
146
Figure 75. Sampling of Data and Parity Bit
147
Figure 76. Stop Bit Sampling and Next Start Bit Sampling
147
SPI Mode
148
SPI Clock Formats and Timing
148
Table 26. CPOL Functionality
148
Figure 77. SPI Clock Formats When UCPHA = 0
149
Figure 78. SPI Clock Formats When UCPHA = 1
150
Receiver Time out (RTO)
151
Figure 79. Example for RTO in USART
151
Table 27. Example Condition of RTO
151
Register Map
152
Table 28. USART Register Map
152
Register Description
153
Baud Rate Settings (Example)
160
Table 29. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies
160
0% Error Baud Rate
161
Figure 80. 0% Error Baud Rate Block Diagram
161
16 Crc
162
Block Diagram
162
Figure 81. CRC Block Diagram
162
Table 30. CRC Mode
162
Register Map
163
Table 31. CRC Register Map
163
Register Description
164
Polynomial
166
17 Power down Operation
167
Peripheral Operation in IDLE/ STOP Mode
167
Table 32. Peripheral Operation Status During Power-Down Mode
167
IDLE Mode
168
Figure 82. IDLE Mode Release Timing by an External Interrupt
168
STOP Mode
169
Figure 83. STOP Mode Release Timing by External Interrupt
169
Released Operation of STOP Mode
170
Figure 84. STOP Mode Release Flow
170
Register Map
171
Register Description
171
Table 33. Power-Down Operation Register Map
171
18 Reset
172
Reset Block Diagram
172
Figure 85. Reset Block Diagram
172
Table 34. Hardware Setting Values in Reset State
172
Power on Reset
173
Figure 86. Fast VDD Rising Time
173
Figure 87. Internal RESET Release Timing on Power-Up
173
Figure 88. Configuration Timing When Power-On
174
Figure 89. Boot Process Waveform
174
Table 35. Boot Process Description
175
External Resetb Input
176
Figure 90. Timing Diagram after RESET
176
Figure 91. Oscillator Generating Waveform Example
176
Low Voltage Reset Process
177
Figure 92. Block Diagram of LVR
177
Figure 93. Internal Reset at Power Fail Situation
177
LVI Block Diagram
178
Figure 94. Configuration Timing When LVR RESET
178
Figure 95. LVI Block Diagram
178
Register Map
179
Reset Operation Register Description
179
Table 36. Reset Operation Register Map
179
19 Memory Programming
182
Flash Control and Status Registers
182
Register Map
182
Table 37. Flash Control and Status Register Map
182
Register Description
183
Figure 96. Read Device Internal Checksum (Full Size)
186
Figure 97. Read Device Internal Checksum (User Define Size)
187
Table 38. Program and Erase Time
188
Memory Map
189
Flash Memory Map
189
Figure 98. Flash Memory Map
189
Figure 99. Address Configuration of Flash Memory
189
Serial In-System Program Mode
190
Flash Operation
190
Figure 100. the Sequence of Page Program and Erase of Flash Memory
190
Figure 101. the Sequence of Bulk Erase of Flash Memory
191
Mode Entrance Method of ISP Mode
195
Mode Entrance Method for ISP
195
Figure 102. ISP Mode
195
Table 39. Operation Mode
195
Table 40. Mode Entrance Method for ISP
195
Security
196
Table 41. Security Policy Using Lock Bits
196
Configure Option
197
Password Function
199
Table 42. Security Mode Using Password Lock Bit
199
Figure 103. Using OCD/E-PGM+/E-GANG4/E-GANG6
200
20 Electrical Characteristics
201
Absolute Maximum Ratings
201
Recommended Operating Conditions
201
Table 43. Absolute Maximum Ratings
201
Table 44. Recommended Operating Conditions
201
A/D Converter Characteristics
202
Table 45. A/D Converter Characteristics
202
VDC1.55 Reference Voltage Characteristics
203
Power on Reset Characteristics
203
Table 47. VDC1.55 Reference Voltage Characteristics
203
Table 48. Power-On Reset Characteristics
203
Low Voltage Reset and Low Voltage Indicator Characteristics
204
Table 49. LVR and LVI Characteristics
204
High Speed Internal RC Oscillator Characteristics
205
Low Speed Internal RC Oscillator Characteristics
205
Table 50. High Speed Internal RC Oscillator Characteristics
205
Table 51. Low Speed Internal RC Oscillator Characteristics
205
DC Characteristics
206
Table 52. DC Characteristics
206
AC Characteristics
207
Figure 104. AC Timing
207
Table 53. AC Characteristics
207
USART Characteristics
208
Table 54. USART Timing Characteristics in SYNC. or SPI Mode Operations
208
Figure 105. SPI Master Mode Timing (UCPHA = 0, MSB First)
209
Figure 106. Spi/Synchronous Master Mode Timing (UCPHA = 1, MSB First)
209
Figure 107. SPI Slave Mode Timing (UCPHA = 0, MSB First)
210
Figure 108. Spi/Synchronous Slave Mode Timing (UCPHA = 1, MSB First)
210
SPI Characteristics
211
Figure 109. SPI0/1 Timing
211
Table 55. SPI Characteristics
211
I2C Characteristics
212
Figure 110. I2C Timing
212
Table 56. I2C Characteristics
212
Data Retention Voltage in Stop Mode
213
Figure 111. Stop Mode Release Timing When Initiated by an Interrupt
213
Figure 112. Stop Mode Release Timing When Initiated by RESETB
213
Table 57. Data Retention Voltage in Stop Mode
213
Internal Flash ROM Characteristics
214
Input/Output Capacitance
214
Table 58. Internal Flash Rom Characteristics
214
Table 59. Input / Output Capacitance
214
Main Clock Oscillator Characteristics
215
Figure 113. Crystal/Ceramic Oscillator
215
Figure 114. External Clock
215
Table 60. Main Clock Oscillator Characteristics
215
Sub-Clock Oscillator Characteristics
216
Figure 115. Crystal Oscillator
216
Figure 116. Crystal Oscillator
216
Table 61. Sub Clock Oscillator Characteristics
216
Main Oscillation Stabilization Characteristics
217
Sub-Oscillation Characteristics
217
Figure 117. Clock Timing Measurement at XIN
217
Figure 118. Clock Timing Measurement at SXIN
217
Table 62. Main Oscillation Stabilization Characteristics
217
Table 63. Sub Oscillation Stabilization Characteristics
217
Operating Voltage Range
218
Recommended Circuit and Layout
218
Figure 119. Operating Voltage Range
218
Figure 120. Recommended Voltage Range
218
Typical Characteristics
219
Figure 121. RUN (IDD1) Current
219
Figure 122. IDLE (IDD2) Current
220
Figure 123. SUB RUN (IDD3) Current
220
Figure 124. SUB IDLE (IDD4) Current
221
Figure 125. SUB IDLE (IDD4) Current
221
21 Package Information
222
16 SOPN Package Information
222
Figure 126 16 SOPN Package Outline
222
20 TSSOP Package Information
223
Figure 127. 20 TSSOP Package Outline
223
20 SOP Package Information
224
Figure 128. 20 SOP Package Outline
224
24 QFN Package Information
225
Figure 129. 24 QFN Package Outline
225
28 SOP Package Information
226
Figure 130. 28 SOP Package Outline
226
32 LQFP Package Information
227
Figure 131. 32 LQFP Package Outline
227
22 Development Tools
228
Compiler
228
OCD (On-Chip Debugger) Emulator and Debugger
228
Figure 132. Debugger (OCD1/OCD2) and Pinouts
228
Programmers
229
OCD Emulator
229
Gang Programmer
229
Figure 133. E-PGM+ (Single Writer) and Pinouts
229
Flash Programming
230
On-Board Programming
230
Figure 134. E-Gang4 and E-Gang6 (for Mass Production)
230
Table 64. Pins for Flash Programming
230
Circuit Design Guide
231
Figure 135. PCB Design Guide for On-Board Programming
231
On-Chip Debug System
232
Figure 136. On-Chip Debugging System in Block Diagram
232
Table 65. OCD Features
232
Two-Pin External Interface
233
Figure 137. 10-Bit Transmission Packet
233
Figure 138. Data Transfer on Twin Bus
234
Figure 139. Bit Transfer on Serial Bus
234
Figure 140. Start and Stop Condition
234
Figure 141. Acknowledge on Serial Bus
235
Figure 142. Clock Synchronization During Wait Procedure
235
Figure 143. Connection of Transmission
236
23 Ordering Information
237
Table 66. A96G166/A96A166/A96S166 Device Ordering Information
237
Figure 144. A96G166/A96A166/A96S166 Device Numbering Nomenclature
238
Appendix
239
Instruction Table
239
Table 67. Instruction Table
239
Revision History
245
4
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Abov A96G166 Specifications
General
Brand
Abov
Model
A96G166
Category
Computer Hardware
Language
English
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