Abov A96G166 - Page 68

6. Interrupt controller A96G166/A96A166/A96S166 User’s manual
68
EIPOL0H (External Interrupt Polarity 0High Register): A5H
7
6
5
4
3
2
1
0
–
POL6
POL5
POL4
–
–
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
EIPOL0H[7:0]
External interrupt (EINT6, EINT5, EINT4) polarity selection
POLn[1:0]
Description
0
0
No interrupt at any edge
0
1
Interrupt on rising edge
1
0
Interrupt on falling edge
1
1
Interrupt on both of rising and falling edge
Where n =4, 5 and 6
EIFLAG1 (External Interrupt Flag 1 Register): A6H
7
6
5
4
3
2
1
0
T0IFR
FLAG12
FLAG11
FLAG10
FLAGA
FLAG9
FLAG8
FLAG7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
T0IFR
When T0 interrupt occurs, this bit becomes ‘1’. For clearing bit,
write ‘0’ to this bit or auto clear by INT_ACK signal. Writing “1” has
no effect.
0
T0 interrupt no generation
1
T0 interrupt generation
EIFLAG1[6:4]
When an External Interrupt 10 ~ 12 is occurred, the flag becomes
‘1’.The flag is cleared only by writing ‘0’ to the bit or automatically
cleared by INT_ACK signal. Writing “1” has no effect.
0
External interrupt 10 ~ 12 not occurred
1
External interrupt 10 ~ 12 occurred
EIFLAG0[4:0]
When an External Interrupt 7 ~ A is occurred, the flag becomes
‘1’.The flag is cleared only by writing ‘0’ to the bit. So, the flag
should be cleared by software. Writing “1” has no effect.
0
External interrupt 7 ~ A not occurred
1
External interrupt 7 ~ A occurred
EIPOL1 (External Interrupt Polarity 1 Register): A7H
7
6
5
4
3
2
1
0
-
POL12
POL11
POL10
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
EIPOL1[5:0]
External interrupt (EINT12,EINT11,EINT10) polarity selection
POLn[1:0]
Description
0
0
No interrupt at any edge
0
1
Interrupt on rising edge
1
0
Interrupt on falling edge
1
1
Interrupt on both of rising and falling edge
Where n =10, 11 and 12