MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 117
CHAPTER 9 WATCH PRESCALER
9.4 Operations and Setting Procedure
Example
• In sub-CR clock mode
Only the sub-CR clock is used as the input clock of the watch prescaler.
â– Operation Example of Watch Prescaler
Figure 9.4-1 shows an operation example under the following conditions:
1. When a power-on reset occurs
2. When the device transits to the sleep mode during the operation of the interval timer
function in subclock mode or sub-CR clock mode
3. When the device transits to the stop mode during the operation of the interval timer
function in subclock mode or sub-CR clock mode
4. When a request for clearing the counter is issued
The same operation is performed when changing to the watch mode as for when changing to
the sleep mode.
Figure 9.4-1 Watch Prescaler Operation Example
WTIF bit
WTIE bit
2) SLP bit
(STBC register)
3) STP bit
(STBC register)
Counter value
(count down)
0x0000
Oscillation stabilization wait time
1) Power-on reset
Interval time
(WPCR:WTC[2:0] = 0b011)
0xFFFF
Sleep
Stop
Sleep mode
released
by watch interrupt
Stop mode released by external interrupt
• When setting interval time select bits in the watch prescaler control register (WPCR:WTC[2:0]) to "0b011" (2
14
× 2/FCL)
Count value detected in
WPCR:WTC[2:0]
4)
• WPCR:WTC[2:0]
• WPCR:WCLR
• WPCR:WTIF
• WPCR:WTIE
• STBC:SLP
• STBC:STP
: Watch prescaler interrupt interval time select bits in watch prescaler control register
: Watch prescaler clear bit in watch prescaler control register
: Watch prescaler interrupt request flag bit in watch prescaler control register
: Watch prescaler interrupt request enable bit in watch prescaler control register
: Sleep bit in standby control register
: Stop bit in standby control register
Counter cleared
(WPCR:WCLR = 1)
Cleared at interval
setting
Cleared in interrupt
service routine
Cleared by transition
to stop mode
Oscillation
stabilization
wait time
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