Fujitsu 8FX

MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 297
CHAPTER 17 CLOCK SUPERVISOR COUNTER
17.3 Operations
■ Sample Operation Flow Chart of Clock Supervisor
Figure 17.3-6 Sample Operation Flow Chart of Clock Supervisor
Clock supervision starts
Oscillation stabilization
wait time elapses
Set CMCSEL,
TBTSEL[2:0]
and CMCEN
Read CMCEN
CMDR value =
estimate ?
Change target external clock
(Normal oscillation)
Keep main CR clock mode
(The external clock is
oscillating at an abnormal
frequency.)
In main CR clock mode, wait for the elapse of the
specified main clock/subcloc
k oscillation stabilization
wait time by using the time-base timer interrupt or
other methods.
YES
NO
YES
NO
"0"
"1"
"0"
"1"
Keep main CR clock mode
(If the oscillation stabilization wait
time has elapsed but the main
clock/subclock oscillation stabili-
zation bit* is not set to “1”, that
means the external clock is dead
or the external clock frequency is
abnormal.)
Read the main clock /
subclock oscillation
stabilization bit*
Main clock oscillation stabilization bit — SYCC2:MRD
Y
Subclock oscillation stabilization bit — SYCC2:SRDY
*: