MB95630H Series
10 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 2 CPU
2.1 Dedicated Registers
● Carry flag (C)
This flag is set to "1" when a carry from bit7 or a borrow to bit7 occurs due to the result of an
operation. Otherwise, the flag is set to "0". When a shift instruction is executed, the flag is set
to the shift-out value.
Figure 2.1-6 shows how the carry flag is updated by a shift instruction.
Figure 2.1-6 Carry Flag Updated by Shift Instruction
■ Interrupt Acceptance Control Bits
● Interrupt enable flag (I)
When this flag is set to "1", interrupts are enabled and accepted by the CPU. When this flag is
set to "0", interrupts are disabled and rejected by the CPU.
The initial value after a reset is "0".
The SETI and CLRI instructions set and clear the flag to "1" and "0", respectively.
● Interrupt level bits (IL[1:0])
These bits indicate the level of the interrupt currently accepted by the CPU.
The interrupt level is compared with the value of the interrupt level setting register (ILR0 to
ILR5) that corresponds to the interrupt request (IRQ00 to IRQ23) of each peripheral function.
The CPU services an interrupt request only when its interrupt level is smaller than the value of
these bits with the interrupt enable flag set (CCR:I = 1). Table 2.1-3 lists interrupt level
priorities. The initial value after a reset is "0b11".
The interrupt level bits (IL[1:0]) are usually "0b11" when the CPU does not service an interrupt
(with the main program running).
For details of interrupts, see "5.1 Interrupts".
Right-shift (RORC)•Left-shift (ROLC)•
bit0bit7
C
bit0bit7
C
Table 2.1-3 Interrupt Levels
IL1 IL0 Interrupt level Priority
00 0 High
01 1
10 2
1 1 3 Low (No interrupt)
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