MB95630H Series
318 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 18 8/16-BIT PPG
18.6 Operations and Setting Procedure Example
is the value of duty setting is output, the PPGn0 pin is set to "L". If the output level reverse
bit (REV00) is "0", the signal is output to the PPGn0 pin with the polarity unchanged. If it is
set to "1", the polarity is reversed and the signal is output to the PPGn0 pin.
Figure 18.6-6 shows the operation of 16-bit PPG mode.
Figure 18.6-6 Operation of 16-bit PPG Mode
256
255
254
...
2
1
256
255
m=256
n=2
...
21
256
255
(1)
(2) = m
×
T
(1) = n
×
T
α
(2)
Synchronizing with
machine clock
Count clock
(Cycle T)
PEN00
Cycle setup
(PPSn1 and PPSn0)
Duty setup
(PDSn1 and PDSn0)
Counter value
(Normal polarity)
PPGn0
(Reverse polarity)
Downcounter value matches
matches duty setting value
Counter borrow
PPG output source
T: Count clock cycle
m: PPSn1 & PPSn0
n: PDSn1 & PDSn0
α: The value changes depending on the count
clock selected and the start timing.
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