Fujitsu 8FX

MB95630H Series
368 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 20 16-BIT RELOAD TIMER
20.6 Operations and Setting Procedure Example
Figure 20.6-10 Count Operation in Reload Mode (Event Count Mode)
● Operation of one-shot mode
If the reload select bit (RELD) is "0", the value of the 16-bit counter halts at "0xFFFF" when
the 16-bit counter underflows ("0x0000" → "0xFFFF").
An interrupt request is output when the underflow request flag bit (UF) in the 16-bit reload
timer control status register (lower) ch. n (TMCSRLn) is set to "1" with the underflow interrupt
enable bit (INTE) set to "1".
The TOn pin outputs a square waveform indicating that counting is in progress. Figure 20.6-11
shows the count operation in one-shot mode.
Figure 20.6-11 Counter Operation in One-shot Mode (Event Count Mode)
TIn pin
Counter
-1
0000
-1
0000
-1
0000
-1
Data load signal
UF bit
CNTE bit
TRG bit
TOn pin
Reload data Reload data Reload data Reload data
TIn pin
Counter
-1
0000
-1
0000
Data load signal
UF bit
CNTE bit
TRG bit
TOn pin
Reload data Reload data
FFFF FFFF
Wait for start trigger input