Fujitsu 8FX User Manual

MB95630H Series
64 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 4 RESET
4.1 Reset Operation
■ Overview of Reset Operation
Figure 4.1-1 Reset Operation Flow
In any reset, the CPU performs mode fetch after the main CR clock oscillation stabilization
wait time elapses.
■ Effect of Reset on RAM Contents
When a reset occurs, the CPU halts the operation of the command currently being executed,
and enters the reset state. However, during RAM access execution, in order to protect the RAM
access, an internal reset signal synchronized with the machine clock is generated after an RAM
access ends. This function prevents a word-data write operation from being interrupted by a
reset while data of two bytes is being written.
Software reset
Watchdog reset
External reset input
Power-on reset/
low-voltage delection
reset
Released from
external reset?
Sub-CR clock
oscillation stabilization
wait time reset state
Sub-CR clock
oscillation stabilization
wait time reset state
Sub-CR clock
oscillation stabilization
wait time reset state
Capture mode data
Capture reset vector
Capture instruction code from the
address indicated by the reset
vector and execute the instruction.
During reset
Mode fetch
Normal operation
(Run state)
NO
YES
YES
NO
NO
YES
Suppress resets
during RAM access
Supress resets
during RAM access
Sub-CR clock is ready?
Sub-CR clock is ready?
Main CR clock oscillation
stabilization wait time

Fujitsu 8FX Specifications

General

Brand	Fujitsu
Model	8FX
Category	Computer Hardware
Language	English