MB95630H Series
68 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 4 RESET
4.2 Register
[bit1] HWR: Hardware reset flag bit
When this bit is set to "1", that indicates a hardware reset (power-on reset, low-voltage detection reset
(optional), external reset or watchdog reset) other than software reset has occurred. Therefore, when any of
bit4 to bit2 is set to "1", this bit is set to "1" as well.
When a software reset occurs, the bit retains the value that has existed before the software reset occurs.
A read access or a write access (writing "0" or "1") to this bit sets it to "0".
[bit0] SWR: Software reset flag bit
When this bit is set to "1", that indicates a software reset has occurred.
When a hardware reset occurs, the bit retains the value that has existed before the hardware reset occurs.
A read access or a write access (writing "0" or "1") to this bit or a power-on reset sets it to "0".
Note:
Since reading the reset source register clears its contents, save the contents of this
register to the RAM before using those contents for calculation.
bit1 Details
Read access Sets this bit to "0".
Being set to "1" Indicates that the a hardware reset has occurred.
Write access Sets this bit to "0".
bit0 Details
Read access Sets this bit to "0".
Being set to "1" Indicates that the a software reset has occurred.
Write access Sets this bit to "0".
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