MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 69
CHAPTER 4 RESET
4.2 Register
■ State of Reset Source Register (RSRR)
1: Flag set
: Previous state kept
×: Indeterminate
EXTS: When this bit is set to "1", that indicates an external reset has occurred.
WDTR: When this bit is set to "1", that indicates a watchdog reset has occurred.
PONR: When this bit is set to "1", that indicates a power-on reset or low-voltage detection reset (optional) has
occurred.
HWR: When this bit is set to "1", that indicates one of the following reset has occurred: an external reset, a
watchdog reset, a power-on reset or a low-voltage detection reset (optional).
SWR: When this bit is set to "1", that indicates that a software reset has occurred.
Table 4.2-2 State of Reset Source Register
Reset source EXTS WDTR PONR HWR SWR
Power-on reset ××110
Low-voltage detection reset (optional) ××110
Software reset 1
Watchdog reset 1 1
External reset 1 1
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