HP 1660 Series User Manual

44 Set up the Format menu.
aa Press the Format key.
bb Move the cursor to the field showing the channel assignments for the pod under test.
Press the Clear Entry key until the pod channels are all assigned (all asterisks (*)).
Press the Done key.
cc Select Master Clock, then select a double edge for the clock of the pod under test.
Turn off the other clocks.
dd In the Master Clock menu, select Setup/Hold, then select 4.0/0.0 ns for the pod being
tested. Select Done. Select Done again to exit the Master Clock menu.
Troubleshooting
To test the logic analyzer probe cables
5–30

HP 1660 Series Specifications

General

Category	Logic Analyzer
Glitch Trigger	Yes
Pattern Trigger	Yes
State Analysis	Yes
Transitional Timing	Yes
Trigger Modes	Edge, Pattern, Glitch