Renesas H8 Series Hardware Manual

Section 3 Exception Handling
Rev. 7.00 Mar 10, 2005 page 84 of 652
REJ09B0042-0700
Bit 1—Timer C Interrupt Enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC Description
0 Disables timer C interrupt requests (initial value)
1 Enables timer C interrupt requests
Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC Description
0 Disables asynchronous event counter interrupt requests (initial value)
1 Enables asynchronous event counter interrupt requests
For details of SCI3 interrupt control, see section 10.2.6 Serial control register 3 (SCR3).
Interrupt Request Register 1 (IRR1)
Bit
Initial value
Read/Write
7
IRRTA
0
R/(W)
*
6


W
5

1

4
IRRI4
0
R/(W)
*
3
IRRI3
0
R/(W)
*
0
IRRI0
0
R/(W)
*
2
IRREC2
0
R/(W)
*
1
IRRI1
0
R/(W)
*
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC, IRQ
4
, IRQ
3
, IRQ
1
, or IRQ
0
interrupt is requested. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.

Renesas H8 Series Specifications

General

Brand	Renesas
Model	H8 Series
Category	Computer Hardware
Language	English