Renesas H8 Series Hardware Manual

Section 6 ROM
Rev. 7.00 Mar 10, 2005 page 174 of 652
REJ09B0042-0700
6.9 Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
6.9.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode,
or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), and erase block register (EBR) are initialized. In a reset via the
RES pin, the reset
state is not entered unless the
RES pin is held low until oscillation stabilizes after powering on. In
the case of a reset during operation, hold the
RES pin low for the RES pulse width specified in the
AC Characteristics section.
6.9.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00,
erase protection is set for all blocks.

Renesas H8 Series Specifications

General

Clock Speed	Up to 20 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
I/O Ports	Multiple
Timers	8-bit/16-bit timers
ADC	10-bit ADC
Interrupts	Multiple interrupt sources
DMA Channels	Available in some models
Communication Interfaces	UART, SPI, I2C
Package Types	QFP, LQFP