Renesas H8 Series Hardware Manual

Section 9 Timers
Rev. 7.00 Mar 10, 2005 page 323 of 652
REJ09B0042-0700
9.7.3 Operation
16-bit Event Counter Operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter.
Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of
bits ACKL1 and ACKL0 in ECCR.
When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.20 shows an example of the software processing when ECH and ECL are used
as a 16-bit event counter.
Start
End
Clear CH2 to 0
Set ACKL1, ACKL0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
Figure 9.20 Example of Software Processing when Using ECH and ECL as 16-Bit Event
Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset,
and as ACKL1 and ACKL0 are cleared to 00, the operating clock is asynchronous event input
from the AEVL pin (using falling edge sensing). When the next clock is input after the count
value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the
OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting
up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.

Renesas H8 Series Specifications

General

Brand	Renesas
Model	H8 Series
Category	Computer Hardware
Language	English