Appendix D Port States in the Different Processing States
Rev. 7.00 Mar 10, 2005 page 638 of 652
REJ09B0042-0700
Appendix D Port States in the Different Processing States
Table D.1 Port States Overview
Port Reset Sleep Subsleep Standby Watch Subactive Active
P1
7
,
P1
6
*
3
,
P1
4
,
P1
3
High
impedance
Retained Retained High
impedance
*
1
Retained Functions Functions
P3
7
to
P3
0
High
impedance
Retained Retained
High
impedance
*
1
Retained Functions Functions
P4
3
to
P4
0
High
impedance
Retained Retained High
impedance
Retained Functions Functions
P5
7
to
P5
0
High
impedance
Retained Retained High
impedance
*
1
*
2
Retained Functions Functions
P6
7
to
P6
0
High
impedance
Retained Retained High
impedance
*
1
Retained Functions Functions
P7
7
to
P7
0
High
impedance
Retained Retained High
impedance
Retained Functions Functions
P8
7
to
P8
0
High
impedance
Retained Retained
High
impedance
Retained Functions Functions
P9
5
to
P9
0
High
impedance
Retained Retained
High
impedance
*
1
Retained Functions Functions
PA
3
to
PA
0
High
impedance
Retained Retained High
impedance
Retained Functions Functions
PB
7
to
PB
0
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
Notes: 1. High level output when MOS pull-up is in on state.
2. In the HD64F38024 the previous pin state is retained.
3. Not implemented on H8/38124 Group.
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