Renesas H8 Series Hardware Manual

Section 5 Power-Down Modes
Rev. 7.00 Mar 10, 2005 page 126 of 652
REJ09B0042-0700
Bit 2
MSON Description
0 Operation in active (high-speed) mode (initial value)
1 Operation in active (medium-speed) mode
Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0)
These bits select the CPU clock rate (φ
W
/2, φ
W
/4, or φ
W
/8) in subactive mode. SA1 and SA0
cannot be modified in subactive mode.
Bit 1
SA1
Bit 0
SA0 Description
00φ
W
/8 (initial value)
01φ
W
/4
1 * φ
W
/2
*: Don’t care
5.2 Sleep Mode
5.2.1 Transition to Sleep Mode
1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON
bits in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction
is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in
SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed)
mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral
functions are operational. The clock frequency in sleep (medium-speed) mode is determined
by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained.
Furthermore, it sometimes acts with half state early timing at the time of transition to sleep
(medium-speed) mode.

Renesas H8 Series Specifications

General

Brand	Renesas
Model	H8 Series
Category	Computer Hardware
Language	English