Section 6 ROM
Rev. 7.00 Mar 10, 2005 page 189 of 652
REJ09B0042-0700
6.11 Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of the flash memory is partly halted and can be read under low power
consumption.
• Standby mode
All flash memory circuits are halted.
Table 6.23 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize the power supply circuits that were
stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to
STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the external
clock is being used.
Table 6.23 Flash Memory Operating States
Flash Memory Operating State
LSI Operating State PDWND = 0 (Initial value) PDWND = 1
Active mode Normal operating mode Normal operating mode
Subactive mode Power-down mode Normal operating mode
Sleep mode Normal operating mode Normal operating mode
Subsleep mode Standby mode Standby mode
Standby mode Standby mode Standby mode
Watch mode Standby mode Standby mode
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