Section 9 Timers
Rev. 7.00 Mar 10, 2005 page 252 of 652
REJ09B0042-0700
9.2.4 Timer A Operation States
Table 9.3 summarizes the timer A operation states.
Table 9.3 Timer A Operation States
Operation Mode Reset Active Sleep Watch
Sub-
active
Sub-
sleep Standby
Module
Standby
TCA Interval Reset Functions Functions Halted Halted Halted Halted Halted
Clock time base Reset Functions Functions Functions Functions Functions Halted Halted
TMA Reset Functions Retained Retained Functions Retained Retained Retained
Note: When the real-time clock time base function is selected as the internal clock of TCA in
active mode or sleep mode, the internal clock is not synchronous with the system clock, so
it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/φ (s) in
the count cycle.
9.2.5 Application Note
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
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