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Section 3 Exception Handling

Rev. 7.00 Mar 10, 2005 page 79 of 652

REJ09B0042-0700

3.3.2 Interrupt Control Registers

Table 3.3 lists the registers that control interrupts.

Table 3.3 Interrupt Control Registers

Name Abbreviation R/W Initial Value Address

IRQ edge select register IEGR R/W — H'FFF2

Interrupt enable register 1 IENR1 R/W — H'FFF3

Interrupt enable register 2 IENR2 R/W — H'FFF4

Interrupt request register 1 IRR1 R/W

— H'FFF6

Interrupt request register 2 IRR2 R/W

— H'FFF7

Wakeup interrupt request register IWPR R/W

H'00 H'FFF9

Wakeup edge select register WEGR R/W H'00 H'FF90

Note: * Write is enabled only for writing of 0 to clear a flag.

IRQ Edge Select Register (IEGR)

Bit

Initial value

Read/Write



IEG4

R/W

IEG3

R/W

IEG0

R/W



IEG1

R/W

IEGR is an 8-bit read/write register used to designate whether pins

IRQ

and

IRQ

are set to rising edge sensing or falling edge sensing. For the IRQAEC pin edge sensing

specifications, see section 9.7, Asynchronous Event Counter (AEC).

Bits 7 to 5—Reserved

Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.

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