Section 3 Exception Handling
Rev. 7.00 Mar 10, 2005 page 80 of 652
REJ09B0042-0700
Bit 4—IRQ
4
Edge Select (IEG4)
Bit 4 selects the input sensing of the
IRQ
4
pin and
ADTRG
pin.
Bit 4
IEG4 Description
0 Falling edge of
IRQ
4
and
ADTRG
pin input is detected (initial value)
1 Rising edge of
IRQ
4
and
ADTRG
pin input is detected
Bit 3—IRQ
3
Edge Select (IEG3)
Bit 3 selects the input sensing of the
IRQ
3
pin and TMIF pin.
Bit 3
IEG3 Description
0 Falling edge of
IRQ
3
and TMIF pin input is detected (initial value)
1 Rising edge of
IRQ
3
and TMIF pin input is detected
Bit 2—Reserved
Bit 2 is reserved: it can only be written with 0.
Bit 1—IRQ
1
Edge Select (IEG1)
Bit 1 selects the input sensing of the
IRQ
1
pin and TMIC pin.
Bit 1
IEG1 Description
0 Falling edge of
IRQ
1
and TMIC pin input is detected (initial value)
1 Rising edge of
IRQ
1
and TMIC pin input is detected
Bit 0—IRQ
0
Edge Select (IEG0)
Bit 0 selects the input sensing of pin
IRQ
0
.
Bit 0
IEG0 Description
0 Falling edge of
IRQ
0
pin input is detected (initial value)
1 Rising edge of
IRQ
0
pin input is detected
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