Section 12 A/D Converter
Rev. 7.00 Mar 10, 2005 page 407 of 652
REJ09B0042-0700
12.3.3 A/D Converter Operation Modes
A/D converter operation modes are shown in table 12.3.
Table 12.3 A/D Converter Operation Modes
Operation
Mode Reset Active Sleep Watch
Sub-
active
Sub-
sleep Standby
Module
Standby
AMR Reset Functions Functions Retained Retained Retained Retained Retained
ADSR Reset Functions Functions Retained Retained Retained Retained Retained
ADRRH Retained
*
Functions Functions Retained Retained Retained Retained Retained
ADRRL Retained
*
Functions Functions Retained Retained Retained Retained Retained
Note: * Undefined in a power-on reset.
12.4 Interrupts
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2
(IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see section 3.3, Interrupts.
12.5 Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.3 shows the operation timing.
1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN
1
the analog
input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored in ADRRH and ADRRL. At the same time ADSF is cleared to 0, and the A/D converter
goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
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