Renesas H8 Series - Page 136

Section 3 Exception Handling
Rev. 7.00 Mar 10, 2005 page 94 of 652
REJ09B0042-0700
PC contents saved
CCR contents saved
I ← 1
I = 0
Program execution state
No
Yes
Yes
No
[Legend]
PC:
CCR:
I:
Program counter
Condition code register
I bit of CCR
IEN0 = 1
No
Yes
IENDT = 1
No
Yes
IRRDT = 1
No
Yes
Branch to interrupt
handling routine
IRRI0 = 1
No
Yes
IEN1 = 1
No
Yes
IRRI1 = 1
No
Yes
IENEC2 = 1
No
Yes
IRREC2 = 1
Figure 3.3 Flow up to Interrupt Acceptance